Renesas Electronics /R7FA6M5BH /CANFD /CFDCFCC4

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Interpret as CFDCFCC4

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CFE 0 (0)CFRXIE 0 (0)CFTXIE 0 (000)CFPLS0 (00)CFM0 (0)CFITSS 0 (0)CFITR 0 (0)CFIM 0 (000)CFIGCV 0CFTML0 (000)CFDC0CFITT

CFM=00, CFIGCV=000, CFRXIE=0, CFITR=0, CFITSS=0, CFE=0, CFPLS=000, CFTXIE=0, CFIM=0, CFDC=000

Description

Common FIFO Configuration/Control Registers 4

Fields

CFE

Common FIFO Enable

0 (0): FIFO disabled

1 (1): FIFO enabled

CFRXIE

Common FIFO RX Interrupt Enable

0 (0): FIFO interrupt generation disabled for Frame RX

1 (1): FIFO interrupt generation enabled for Frame RX

CFTXIE

Common FIFO TX Interrupt Enable

0 (0): FIFO interrupt generation disabled for Frame TX

1 (1): FIFO interrupt generation enabled for Frame TX

CFPLS

Common FIFO Payload Data Size Configuration

0 (000): 8 bytes

1 (001): 12 bytes

2 (010): 16 bytes

3 (011): 20 bytes

4 (100): 24 bytes

5 (101): 32 bytes

6 (110): 48 bytes

7 (111): 64 bytes

CFM

Common FIFO Mode

0 (00): RX FIFO mode

1 (01): TX FIFO mode

2 (10): CAN – CAN GW FIFO mode

3 (11): Reserved

CFITSS

Common FIFO Interval Timer Source Select

0 (0): Reference clock (× 1 / × 10 period)

1 (1): Bit time clock of related channel (FIFO is linked to fixed channel)

CFITR

Common FIFO Interval Timer Resolution

0 (0): Reference clock period × 1

1 (1): Reference clock period × 10

CFIM

Common FIFO Interrupt Mode

0 (0): RX FIFO mode: RX interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO mode: TX interrupt generated when Common FIFO transmits the last message successfully GW FIFO mode: For RX interrupt flag: Interrupt generated when FIFO counter increments and reaches the value configured in CFIGCV For TX interrupt flag: Interrupt generated when FIFO transmits the last message successfully

1 (1): RX FIFO mode: RX interrupt generated at the end of every received message storage TX FIFO mode: interrupt generated for every successfully transmitted message GW FIFO mode: For RX interrupt flag: Interrupt generated when a message is stored in the FIFO For TX interrupt flag: Interrupt generated when a message is successfully transmitted from the FIFO

CFIGCV

Common FIFO Interrupt Generation Counter Value

0 (000): Interrupt generated when FIFO is 1/8th full

1 (001): Interrupt generated when FIFO is 1/4th full

2 (010): Interrupt generated when FIFO is 3/8th full

3 (011): Interrupt generated when FIFO is 1/2 full

4 (100): Interrupt generated when FIFO is 5/8th full

5 (101): Interrupt generated when FIFO is 3/4th full

6 (110): Interrupt generated when FIFO is 7/8th full

7 (111): Interrupt generated when FIFO is full

CFTML

Common FIFO TX Message Buffer Link

CFDC

Common FIFO Depth Configuration

0 (000): FIFO Depth = 0 messages

1 (001): FIFO Depth = 4 messages

2 (010): FIFO Depth = 8 messages

3 (011): FIFO Depth = 16 messages

4 (100): FIFO Depth = 32 messages

5 (101): FIFO Depth = 48 messages

6 (110): FIFO Depth = 64 messages

7 (111): FIFO Depth = 128 messages

CFITT

Common FIFO Interval Transmission Time

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